It may be recalled that the size of a device defines the gate length of CMOS transistors. The transistors produced using CMOS technology below 45 nanometers, and, more particularly, 32 nanometers form the subject of numerous publications, in particular “32 nm General Purpose Bulk CMOS Technology for High Performance Application at Low Voltage (Electron Devices Meeting, 2008, IEDM 2008, IEEE International, p. 1 to 4, ISSN: 8164-2284, ISBN: 978-1-4244-2377-4, published on 15-17 Dec. 2008)”, “32 nm Gate-First High-k/Metal-Gate Technology for High Performance Low Power Applications (Electron Devices Meeting, 2008, IEDM 2008, IEEE International, p. 1 to 4, ISSN: 8164-2284, ISBN: 978-1-4244-2377-4, published on 15-17 Dec. 2008)” and “A 32 nm Logic Technology Featuring 2nd-Generation High-k+Metal-Gate Transistors, Enhanced Channel Strain and 0.171 μm2 SRAM Cell Size in a 291 Mb Array (Electron Devices Meeting, 2008, IEDM 2008, IEEE International, p. 1 to 4, ISSN: 8164-2284, ISBN: 978-1-4244-2377-4, published on 15-17 Dec. 2008)”.
Moreover, studies of characteristics and performance of these transistors have also been published, such as, for example, in the publications “Physical and Electrical Analysis of the Stress Memorization Technique (SMT) using Poly-Gates and its Optimization for Beyond 45 -nm High-Performance Application (Electron Devices Meeting, 2008, IEDM 2008, IEEE International, p. 1 to 4, ISSN: 8164-2284, ISBN: 978-1-4244-2377-4, published on 15-17 Dec. 2008)” and “Gate Length Scaling and High Drive Currents Enabled for High Performance SOI Technology using High-k/Metal Gate (Electron Devices Meeting, 2008, IEDM 2008, IEEE International, p. 1 to 4, ISSN: 8164-2284, ISBN: 978-1-4244-2377-4, published on 15-17 Dec. 2008)”.
For example, “Scaling of 32 nm Low Power SRAM with High-K Metal Gate (Electron Devices Meeting, 2008, IEDM 2008, IEEE International, p. 1 to 4, ISSN: 8164-2284, ISBN: 978-1-4244-2377-4, published on 15-17 Dec. 2008)” and “Demonstration of Highly Scaled FinFET SRAM Cells with High-K/Metal Gate and Investigation of Characteristic Variability for the 32 nm node and beyond (Electron Devices Meeting, 2008, IEDM 2008, IEEE International, p. 1 to 4, ISSN: 8164-2284, ISBN: 978-1-4244-2377-4, published on 15-17 Dec. 2008)” disclose several analyses of the performance of static random access memory (SRAM) manufactured based upon 32-nanometer CMOS technology transistors. For example, “22 nm Technology Compatible Fully Functional 0.1 μm2 6T-SRAM Cell (Electron Devices Meeting, 2008, IEDM 2008, IEEE International, p.1 to 4, ISSN: 8164-2284, ISBN: 978-1-4244-2377-4, published on 15-17 Dec. 2008)” discloses several analyses of the performance of memories of SRAM manufactured based upon 22-nanometer CMOS technology transistors.